• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    The invention relates to a method for managing the endurance of a non-volatile rewritable memory comprising a plurality of memory cells (10) each comprising an ordered stack of a lower electrode (12), a layer of dielectric material (13) and an upper electrode (11), the dielectric material of each stack being able to switch between a highly resistive state (HRS) and a weakly resistive state (LRS), or vice versa, to allow writing in the cell memory or erasure of said memory cell. This method comprises the following operations: at the end of each write and erase cycle of the memory cell, read conditions for erasure of said memory cell during the last erasure operation of the cycle, and comparison said erase conditions read with a predetermined median erase value; and determining write conditions of the memory cell from the results of the comparison, said writing conditions being applied to the electrodes of the stack during the write operations of the next write and erase cycle in order to to limit the generation of defects in the dielectric material.
    公开号:FR3066308A1
    申请号:FR1754043
    申请日:2017-05-09
    公开日:2018-11-16
    发明作者:Gabriel Molas；Michel Harrand；Elisa Vianello；Celine Nail
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR MANAGING THE ENDURANCE OF A NON-VOLATILE REWRITE MEMORY AND DEVICE FOR
    PROGRAMMING SUCH A MEMORY
    TECHNICAL AREA
    The present invention relates to a method for managing the endurance of a non-volatile rewritable memory. The invention also relates to a device for programming such a non-volatile rewritable memory. The invention finds applications in the field of non-volatile rewritable memories and, more specifically, that of resistive memories of the OxRRAM (“Oxide-based Resistive RAM” and CBRAM (“Conductive Bridging RAM”) type.
    STATE OF THE ART
    In the field of non-volatile rewritable memories, different types of memories are used depending on the applications and the targeted performances. The most commonly used memories, in particular in digital cameras, cell phones, laptops, USB keys, and other portable devices, are memories called "Flash memories". Flash memories offer, in particular, a high integration density, great impact resistance and good durability.
    Most commercially available non-volatile Flash memories use charge storage as the principle for encoding information. In practice, a charge trapping layer (generally polysilicon, or a dielectric such as SiN) is encapsulated between two dielectrics in the gate stack of an MOS transistor. The presence or absence of charge in this medium modifies the conduction of the MOS transistor and makes it possible to code the state of the memory.
    However, the evolution of microelectronics requires ever more miniaturization of the components and, in particular, non-volatile rewritable memories. However, the miniaturization of Flash technology is limited, in particular by the fact that the thickness of the charge trapping layer cannot be reduced below a minimum value (of the order of 6 nm) under penalty of reducing the information retention time. Recently, a new type of memories, called resistive memories, have appeared to replace Flash memories. These resistive memories are not based on the charge trapping of the transistor gates, but on a change of state of a resistive block. Resistive memories, in particular resistive memories based on oxide, called OxRRAM, and resistive memories based on material with ionic conduction, called CBRAM, are based on a change of the state of resistance (strong or weak resistance) d 'an active material integrated between two metal electrodes. This new type of memory allows not only a high integration density, but also a high operating speed, great endurance and good compatibility with the manufacturing processes currently used in the microelectronics industry, in particular with the manufacturing processes. end of line of CMOS technology.
    A resistive memory generally comprises a plurality of memory cells, also called memory points. Each memory cell 10 comprises a stack of first and second electrodes, generally made of metal, and of a layer of active material, for example a metal oxide, placed between the two electrodes. An example of a resistive memory cell is shown in FIG. 1. This resistive memory comprises a first electrode 11, a second electrode 12 and a layer of dielectric material 13 arranged between the first and second electrodes. The second electrode 12 of the resistive memory is formed in contact with a connector substrate 14 ensuring electrical contact between a programming device and the stack. The programming device makes it possible to control the programming conditions, for example the programming voltage, applied to the electrodes 11 and 12 of the stack.
    The layer of dielectric material 3, also called active layer, is capable of reversibly switching between two resistance states which correspond to the logical values "0" and "1" used to code an information bit. Thus, a resistive memory stack can switch from a weakly resistive state LRS (“Low Résistance State” in Anglo-Saxon terms) to a strongly resistive state HRS (“High Résistance State” in Anglo-Saxon terms) by the application a first voltage VRESET between the first 11 and the second 12 electrodes, and switch back from the highly resistive state HRS to the weakly resistive state LRS by applying a second voltage VSET between the first and second electrodes. In particular, information is written to the memory cell by toggling the layer of dielectric material from the highly resistive HRS state, also called "OFF" state, to the low resistive LRS state, or "ON" state. Conversely, information can be erased from the memory cell by switching the dielectric material layer from the LRS state to the HRS state. The write operation in the memory cell is called "SET"; the erase operation of said memory cell is called "RESET".
    Thus, during a writing operation, the dielectric material comprises a first resistance value and, during an erasing operation, it comprises a second resistance value, less than the first resistance value. The change in resistance of the dielectric material is governed by the formation and rupture of a conductive filament of nanometric section between the two electrodes 11-12. In the current state of knowledge, this filament seems to be due to different phenomena, depending on the type of material used for the layer of active material. In particular, in a resistive memory of the OxRRAM type in which the layer of dielectric material is based on oxide, the change in resistive state seems to be explained by the formation of a filament of oxygen vacancies within said layer of dielectric material. In a resistive memory of the CBRAM type, in which the layer of dielectric material comprises an ion-conducting material forming a solid ion-conducting electrolyte disposed between an electrode forming an inert cathode and an electrode comprising a portion of ionizable metal, the change of resistive state seems to be explained by the formation of a conductive filament within the layer of dielectric material.
    However, in resistive memories, there is a certain variability in the resistance levels, both in the weakly resistive LRS state and in the highly resistive HRS state. Indeed, with each write and erase memory operation, the values of the resistance Roff in the highly resistive state HRS and the values of the resistance Ron in the weak resistive state LRS fluctuate, as represented by the fluctuation curves of the resistances Roff and Ron of figure 2.
    In addition, as the memory is written and erased, the resistance levels of the dielectric material drift, deviating more and more from the resistance values of the first cycles, as shown in the figure. 2. Because of these drifts, the writing and erasing conditions - for example the writing voltage or the erasing voltage - must be modified to allow writing or erasing of a dielectric material. These modifications generally consist in applying a very strong tension or, on the contrary, very weak. However, the application of writing or erasing conditions that are too weak prevents any writing and the application of writing or erasing conditions that are too strong generates defects in the dielectric material, which degrades said dielectric material. The performance of resistive memories therefore tends to deteriorate more and more over the writing and erasing cycles. The endurance performance of these memories is therefore relatively limited.
    To remedy this endurance problem and thus lengthen the life of resistive memories, it is known to use a process called "smart programming" which aims to compensate for the defects accumulated during several write cycles and clearing the memory. For this, the smart programming method proposes to apply a programming voltage which gradually increases from a deliberately too low value to a value where the dielectric material reaches a target resistance value. In other words, this method proposes to determine a target resistance value considered as the optimal resistance value to be reached. A compensation voltage - or a duration or a number of pulses at constant voltage level - intended to reduce the probability of generating many faults in the dielectric material, is then applied from a low value which is increased step by step up to resistance reaches the predetermined target value. The compensation conditions (voltage or pulse duration) are applied to limit the defects within the dielectric material both in its weakly resistive state and in its highly resistive state.
    FIGS. 3A and 3B represent curves showing the evolution, respectively, of the resistance values of the dielectric material and of the values of the compensation voltage applied to the memory, during a large number of write cycles and erasure, when a smart programming process is used. It is understood from these curves that, when a write compensation voltage (“set” curve) and erasure (“reset” curve) is applied, the value of the resistors in the H RS state and in the LRS state of the dielectric material increases. However, this increase in resistance values is only temporary, the resistance values again decreasing rapidly during the cycles following the application of the compensation voltage. Indeed, the voltage compensation being generally carried out only after a certain number of cycles - for example around 102 and 104 cycles in FIGS. 3A-3B - the memory is already greatly deteriorated when the compensation voltage is applied . This write and erase compensation therefore camouflages the faults generated during the write and erase cycles, without however repairing them. Indeed, the defects of the dielectric material at the origin of the modification of the resistive levels of the dielectric material are irreversible. It is therefore not possible to repair them, but only to compensate them by writing more and more loudly - and therefore by degrading more and more the dielectric material.
    Indeed, the application of strong write and erase compensation conditions, in order to compensate for the defects generated in the dielectric material, has the effect of generating new defects within said dielectric material.
    SUMMARY OF THE INVENTION
    To respond to the problem mentioned above of compensating for faults in the dielectric material, the applicant proposes a method for managing the endurance of a resistive memory in which the conditions for writing the memory to be applied during the cycle to Coming (or following cycle) are determined according to the erasure conditions applied during the previous cycle, so as to limit the drifts of resistance of the dielectric material at each cycle and, thus, slow down the degradation of the memory.
    According to a first aspect, the invention relates to a method for managing the endurance of a non-volatile rewritable memory comprising a plurality of memory cells each comprising an ordered stack of a lower electrode, of a layer of dielectric material and of an upper electrode, the dielectric material of each stack being able to switch between: - a highly resistive state, and - a weakly resistive state, a switching between the highly resistive state and the weakly resistive state allowing writing in the memory cell and a switching between the weakly resistive state and the highly resistive state authorizing an erasure in said memory cell,
    This method is characterized by the fact that it includes the following operations: - at the end of each write and erase cycle of the memory cell, reading of erasure conditions of said memory cell during the last operation erasing the cycle, and comparing said erasure conditions read with a predetermined median erasure value; and determination of writing conditions of the memory cell from the results of the comparison, said writing conditions being applied to the electrodes of the stack during the writing operations of the following writing and erasing cycle so as to to limit the generation of faults in the dielectric material.
    Adjusting the writing conditions of the memory cell makes it possible to slow down the generation of faults in the dielectric material at each write and erase cycle and, thus, to stabilize the resistance drifts of each memory cell of resistive memory. This stability of resistance drifts increases the endurance of memory and therefore its lifespan.
    According to a variant, the writing conditions comprise a value of writing voltage applied between the electrodes of each memory cell, for a constant period, so that the dielectric material switches from the highly resistive state to the weakly resistive state.
    According to another variant, the writing conditions include a duration of application of a voltage of constant value between the electrodes of each memory cell, so that the dielectric material switches from the highly resistive state to the weakly resistive state.
    Advantageously, the median erasure value follows a predetermined dependence law, linking the writing conditions and the erasing conditions. The dependence law can be calibrated prior to any writing and erasing cycle. This dependence law makes it possible to adapt the method of the invention to all types of resistive memories, each type of resistive memory having its own dependence law.
    According to certain embodiments, each write and erase cycle comprises an alternating set of at least one write operation and at least one erase operation. Thus, the term “cycle” defines a set consisting of at least one write operation and at least one operation for erasing data from a memory cell of the resistive memory, a write operation succeeding each erase operation. In one of the embodiments, the write and erase cycle comprises a single write operation and a single erase operation. This embodiment provides good precision in determining the writing conditions. In another embodiment, the write and erase cycle includes several write operations and several erase operations, an erase operation alternating with a write operation. This embodiment offers a compromise between precision and speed of programming.
    Advantageously, the erasure conditions read are stored at least partially until the next write and erase cycle, in at least one memory cell of the non-volatile rewritable memory.
    According to a second aspect, the invention relates to a device for programming a non-volatile rewritable memory implementing the above method.
    According to certain embodiments, the programming circuit comprises a plurality of voltage generators capable of each generating at least one write and / or erase voltage value.
    According to other embodiments, the programming circuit comprises at least one voltage generator connected to dividing bridges.
    These different embodiments make it possible to vary the write and / or erase voltage so that the voltage applied to the electrodes is as close as possible to the determined voltage value.
    According to still other embodiments, the programming circuit comprises at least one voltage generator connected to at least one counter and / or a clock capable of modulating a duration of application of a constant voltage on the electrodes.
    These embodiments make it possible to vary the writing and erasing conditions with a simple and inexpensive circuit.
    BRIEF DESCRIPTION OF THE FIGURES Other advantages and characteristics of the invention will appear on reading the description, illustrated by the figures in which: - Figure 1, already described, schematically represents an example of a memory cell of a memory resistive; - Figure 2, already described, shows examples of the evolution of the resistances Roff and Ron of a memory cell during cycles; - Figures 3A and 3B, already described, show examples of the evolution of the resistances Roff and Ron, as a function of the write and erase voltages, during an implementation of the smart programming method; - Figures 4A and 4B show examples of evolution and distribution of resistors Roff and Ron, during an implementation of the method according to the invention; - Figure 5 shows an example of a dependency law used in the method according to the invention; - Figures 6A and 6B schematically represent two modes of implementation of the adjustment of the writing conditions of the method of the invention; - Figure 7 shows an example of an LD dependence law constructed experimentally for a particular CBRAM memory.
    DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT
    An example of a method for managing the endurance of a resistive memory is described in detail below, with reference to the accompanying drawings. This example illustrates the characteristics and advantages of the invention. It is however recalled that the invention is not limited to this example.
    In the figures, identical elements are identified by identical references. For reasons of readability of the figures, the size scales between the elements represented are not respected.
    The endurance management method according to the invention is implemented in a resistive memory comprising a plurality of memory cells, of the type shown in FIG. 1 described above. Each memory cell 10 comprises an ordered stack, formed of a lower electrode 12, an upper electrode 11 and a layer of dielectric material 13. This stack is associated with a programming circuit 15 capable of applying a potential difference between the two electrodes 11 and 12. Several memory cells 10 are arranged one next to the other, on one or more stages, to form a resistive memory.
    The layer of dielectric material 13, for example a layer of Hafnium Oxide (HfO2), is capable of passing from a weak resistive state LRS to a highly resistive state HRS, and vice versa, under the effect of a voltage applied between the upper and lower electrodes. In the weakly resistive state, the dielectric material has a Ron resistance; in the highly resistive state, the dielectric material has a resistance Roff, greater than Ron. Switching the dielectric material from the highly resistive state HRS to the weakly resistive state LRS makes it possible to write data; switching the dielectric material from the weakly resistive state LRS to the highly resistive state HRS makes it possible to erase the data. Each phase of erasing a piece of data from the memory cell follows a phase of writing said piece of data. An alternating set of write and erase phases form a write and erase cycle. A write and erase cycle, also called a cycle, can thus include a write phase followed by an erase phase; it can also include an alternation of several writing phases and several erasing phases.
    The method of the invention proposes to limit the drifts of the resistances Roff and Ron at each cycle so as to reduce, or even prevent, the formation of defects in the dielectric material 13. For this, the method of the invention proposes to determine the writing conditions to apply to a cycle according to the erasure conditions applied to the previous cycle. Indeed, the fact of writing in the memory cell with writing conditions established as a function of the erasure conditions of the preceding cycle allows the resistance Ron of the dielectric material in the weakly resistive state LRS to fluctuate around a Ronmed median resistance value. Insofar as the resistance Ron fluctuates around a median resistance value Ronmed and insofar as the resistance value Roff of the dielectric material in the highly resistive state HRS is determined for each cycle - as explained below - the Roff resistance value fluctuates around a median Roffmed resistance value.
    FIG. 4A represents examples of fluctuation of the Ron and Roff resistances of the same memory cell, over several cycles. FIG. 4B represents examples of the cumulative distribution of the values of the resistances Ron and Roff. In particular, FIG. 4A represents the curve of the resistance values Roff which fluctuate around a first median resistance value Roffmed and the curve of the resistance values Ron which fluctuate around a second median resistance value Ronmed.
    The filament within the dielectric material having a variable shape at the end of each write operation and erasure operation, the resistance of said dielectric material, which depends on the fluctuation of the filament, has stochastic values, both at highly resistive state than weakly resistive state. The method of the invention proposes to adjust the writing conditions to be applied during the writing operation or operations of the next cycle as a function of the erasing conditions applied during the last erasing operation of the previous cycle, so as to compensate, at each cycle, for fluctuations in said filament. Thus, the fact of determining, at each cycle, the writing conditions to be used in the following writing operation makes it possible to write the data with optimal writing conditions which limit the generation of faults in the memory cell. The writing conditions to be applied to the next cycle are adjusted by comparing the erasing conditions applied during the last erasing operation of the previous cycle with a predetermined median erasing value. This median erasure value can be the erasure value corresponding to the median resistance value Ftonmed shown in FIG. 4A. The median erasure value follows a dependency law Ld linking the writing conditions to the erasing conditions. This dependence law makes it possible, from the erasure conditions of the memory cell applied to a cycle n-1, to define the writing conditions to be applied to the following cycle n. The writing conditions are therefore adjusted according to the erasure conditions read. An example of a dependency law Ld will be described in more detail below, in relation to FIG. 5. According to a variant, the dependence law Ld can be discretized; the erase condition is then compared with a median value of the erase conditions and the write conditions to be applied to the next write operation are determined as a function of this median value.
    According to certain embodiments, the writing and erasing conditions can be a voltage, respectively, of writing and erasing, that is to say a potential difference applied between the two electrodes of a stack. to allow writing or erasing data on / from the memory cell. In such embodiments, the voltage value applied between the electrodes is variable and the duration of application of this voltage is constant. According to other embodiments, the writing and erasing conditions can be the duration of application of the voltage to the electrodes - the duration can also correspond to a number of pulses applied to the electrodes. In these embodiments, the duration (or the number of pulses) is variable and the value of the applied voltage is constant. Indeed, a person skilled in the art will understand that, due to the known equivalence in the field of resistive memories between the voltage level and the duration of the power-up, it is possible to apply to the electrodes, either a voltage of constant value with a variable duration, ie a voltage of variable value but with a constant duration.
    In the examples which will now be described, the writing and / or erasing conditions will be the variable voltage applied between the electrodes of a memory cell, it being understood that similar examples could be implemented with a duration of variable application (or number of pulses) and a constant voltage value.
    FIG. 5 represents an example of a dependence law Ld between the erasing voltage Vreset and the writing voltage Vset of a memory cell. According to this example, if the erase voltage read at the end of cycle n-1 has the value Vresetl, then the value of the write voltage at cycle n will be Vsetl, the value Vsetl being defined as a function of the value Vresetl and the Ld dependency law. Similarly, if the erase voltage read at the end of cycle n-1 has the value Vreset2, then the value of the write voltage, defined as a function of the value Vreset2 and the dependence law Ld, will be Vset2 in cycle n. Thus, the higher the value of the voltage required to erase data during one cycle, the higher the value of the voltage required to rewrite data during the next cycle. Conversely, the lower the value of the voltage required to erase data during one cycle, the lower the value of the voltage required to write data to the next cycle.
    The fact of applying, at each cycle, a writing voltage corresponding to the erasing voltage which it took in the previous cycle to reach the target resistance (i.e. the resistance Roff allowing the erasure) makes it possible to limit the faults generated in the dielectric material by taking account of the stochastic evolution of the state of resistance of the dielectric material.
    To optimize the process of the invention, it is preferable that the memory cell is erased optimally during the previous cycle. To erase the memory cell in an optimal manner, that is to say with a resistance value Roff adapted to the state of the dielectric material, several methods can be implemented.
    For example, the smart programming method described in the prior art can be implemented so as to gradually reach the resistance value Roff at which the memory cell is erased. As soon as the Roff value is reached, the value of the erase voltage allowing this Roff resistance value to be reached is read and stored for later use in the write voltage determination operation. Other methods can also be implemented to allow the memory cell to be erased in an optimal manner, for example, a method in which the conditions of the determination of the conditions at the end of each write and erase cycle are determined. 'erasure which will be implemented in the next write and erase cycle. These erasure conditions are determined so that, in the highly resistive HRS state, the resistance Roff of the dielectric material fluctuates around a median resistance value Roffmed. Such a method can, for example, propose to: read, at the end of a write operation of a cycle n-1, the resistance value of the dielectric material; comparing this resistance value read with predetermined reference values; determine erasure conditions from the result of this comparison; apply to the memory cell, during the erasing operation of the following cycle n, the determined erasing conditions; memorize these erasing conditions, for example the value of the erasing voltage enabling the resistance value Roff to be reached, so that they can be used later in the operation of determining the writing voltage. Those skilled in the art will understand that either of the methods mentioned above can be implemented, as well as other methods as soon as these other methods make it possible to achieve the best Roff resistance value. suitable for erasing the data entered in the memory cell. The method to be applied to determine the erasure conditions can be chosen, for example, taking into account any constraints, such as constraints of time, voltage, algorithm, etc.
    The erasing conditions, for example the erasing voltage, which make it possible to reach the resistance value Roff are the basic data for determining the writing conditions of the memory cell during the next cycle. These writing conditions for the next cycle (or following cycle) are defined as being the image of the conditions for erasing from the previous cycle by the dependency law Ld.
    The dependence law Ld between the erasure conditions and the writing conditions is a predefined law, determined during a preliminary calibration step. The law of dependence differs according to memory technology. For example, a resistive memory of the OxRRAM type with a layer of Hafnium Oxide as dielectric material will present a law of dependence different from that of a CBRAM memory with a layer of Germanium Sulfide. Each type of resistive memory therefore responds to a predetermined dependence law, recorded within said memory to allow the determination of the writing conditions.
    In certain embodiments, the dependence law Ld links the erasure voltage of a cycle with the write voltage of a following cycle. In other embodiments, the dependence law relates the duration of application (or the number of pulses) of a writing voltage of constant value, with the duration of application (or the number of pulses ) a constant value erase voltage.
    Whatever the embodiment, the dependence law can be determined by calculations, for example, by simulation using RRAM models. This dependence law Ld can also be determined experimentally, by successive measurements.
    The dependence law Ld can, for example, be determined according to the following experimental method: Starting from written cells (LRS state), different erasure conditions are applied, for example different values of Vreset voltage or Treset time. We then reach the HRS state. On these erased cells, write pulses are applied, with a constant pulse time, increasing the write voltage with each pulse. The voltage from which the memory cell is written (therefore switches to the LRS state) is defined as the write voltage. An example of an experimental Vset curve as a function of Vreset for an AI2O3 / CuTe CBRAM memory is shown in FIG. 7. This curve constitutes an example of the dependence law Ld used in the method of the invention.
    Whatever the dependence law chosen, the method according to the invention comprises the following steps: at the end of a cycle n-1, reading of the value of the erasing voltage applied during the last erasing operation; recording this erasing voltage value in at least one memory cell of the resistive memory; determination of the writing conditions to be used in the following cycle n, from the value of the recorded erasing voltage and from the predefined dependence law; application to the memory cell of the writing conditions determined for cycle n.
    Alternatively, each cycle includes a write operation and an erase operation. The method is then implemented at the end of each erasing operation in order to determine the writing conditions for each writing operation. This variant has the advantage of offering great precision in determining the writing conditions.
    According to another variant, each cycle comprises an alternation of several writing operations and several erasing operations, for example ten erasing operations and ten writing operations. The method is then implemented regularly after several alternate writing and erasing operations in order to determine the writing conditions to be applied to all the writing operations of the following cycle. This variant has the advantage of being faster than the previous variant since the same writing conditions are applied to several writing operations. The operation of reading the value of the conditions for erasing the memory cell in the previous cycle includes a comparison of this value with reference values. These reference values can be generated in a programming circuit described later. When the erasing conditions are the value of the erasing voltage, the comparison can be carried out by means of comparators connected to voltage generators such as those described below.
    As explained above, the erasure conditions read in the previous cycle are stored in memory cells of the resistive memory. According to certain embodiments, the memory space dedicated to the implementation of the method of the invention can be optimized by memorizing, for example, only the conditions of the memory cells considered to be the most sensitive by the user such as, for example , the cells most often erased and rewritten from the resistive memory and / or the memory cells using the highest programming voltages
    Indeed, the method of the invention - with adaptation of the writing conditions - can only be implemented for a fraction of the total memory, which corresponds to a reduced number of memory cells. This reduced number of memory cells can be chosen, by the user, like sensitive cells.
    According to certain embodiments, an associative memory is used to store the addresses and erasure conditions: the “tag” part of this associative memory can, for example, be performed in FteRAM since it is written infrequently. The erasure conditions are coded in SRAM, a technology not subject to wear. The method of the invention is used only on a small portion of the memory because the size of the SRAM memories is greater than that of the ReRAMs.
    According to certain embodiments, the memory space dedicated to the implementation of the method of the invention can be optimized by using the cache memory areas of the resistive memory to temporarily store the values of the erasure conditions and use them at the time where the cache memory must be emptied to store other data there. The cache memory is then used to successively store several data of different types.
    According to certain embodiments, the memory space dedicated to the storage of the conditions read can be optimized by storing only a tendency of the writing conditions to be applied, this tendency being able to be more or less precise. For example, to decrease the number of memory cells necessary for storing the conditions read, it is possible to code, on a single memory cell, the tendencies "increase the writing voltage" and "decrease the writing voltage". By increasing the number of memory cells, the nuance of the trend can be refined; for example, by coding on two memory cells, it is possible to code the information “apply the median tension + n%”, “apply the median tension - n%”, “apply the median tension + 2n%” and “apply the median tension -2n% ".
    The dependence law must also be stored in the resistive memory. However, since this dependence law is valid for all the memory cells of the same memory and during the entire lifetime of said memory, it does not need to be refreshed and can be stored in a read only memory area. . Those skilled in the art will understand that a high number of memory cells dedicated to the implementation of the method of the invention makes it possible to code refined programming conditions. It will also understand that several of the embodiments described above can be implemented simultaneously in order to best optimize the ratio between the memory space dedicated to the implementation of the method and the accuracy of determining the programming conditions. .
    The method according to the invention can be implemented in a device for programming a resistive memory. This device may include a programming circuit, connected to the upper and lower electrodes of each memory cell of the memory.
    According to certain embodiments, the programming circuit comprises a plurality of voltage generators capable of each delivering at least one write and / or erase voltage value different from the voltage value delivered by the other generators. In fact, to apply the write and / or erase voltage values determined by the method of the invention, several voltage generators may be necessary, as shown in FIG. 6A. The programming circuit can then choose, from the voltage generators, the number and the combination of these generators which make it possible to best approach the determined write or erase voltage value. However, in order to limit the number of voltage generators, each generator may include dividing bridges which, by dividing a reference voltage, make it possible to apply the write and / or erase voltage value to the electrodes. closer to the determined value.
    According to certain other embodiments, the programming circuit comprises a single (or more) voltage generator (s) delivering (each) a constant voltage value. This voltage generator is connected to at least one counter and / or a clock capable of controlling the duration or the number of pulses of constant voltage to be applied to the electrodes to obtain a result identical to that which would have been obtained with a voltage value. writing and / or erasing determined in the embodiments where the voltage is variable. An example of application of the number of pulses at a constant voltage, determined with the method according to the invention, for a writing operation is shown diagrammatically in FIG. 6B.
    Thus, the fact of determining, at each cycle, the writing conditions to be used in the next cycle, in correspondence with the erasure conditions in the previous cycle, makes it possible to write the data with optimal conditions which limit the generation of faults in the memory cell. The faults generated in the dielectric material are therefore compensated for each cycle, before the memory has drifted too much. Indeed, the fact of compensating for a drift in the resistance of the dielectric material quickly after the birth of the latter makes it possible to stabilize the state, respectively, of high or low resistance of the dielectric material.
    Thus, the method according to the invention makes it possible to manage the endurance of a resistive memory by determining, at each cycle, the writing conditions of each memory cell in the following cycle. The method according to the invention thus makes it possible to improve the endurance of a resistive memory and, consequently, to increase the lifetime of said memory.
    Although described through a certain number of examples, variants and embodiments, the endurance management method according to the invention and the programming device implementing this method include various variants, modifications and improvements which will appear so obvious to a person skilled in the art, it being understood that these variants, modifications and improvements form part of the scope of the invention, as defined by the claims which follow.
    权利要求:
    Claims (11)
    [1" id="c-fr-0001]
    1. A method for managing the endurance of a non-volatile rewritable memory comprising a plurality of memory cells (10) each comprising an ordered stack of a lower electrode (12), of a layer of dielectric material (13) and an upper electrode (11), the dielectric material of each stack being able to switch between: - a highly resistive state (HRS), and - a weakly resistive state (LRS), a switching between the highly resistive state and the weakly resistive state authorizing a write in the memory cell and switching between the weakly resistive state and the highly resistive state authorizing an erasure in said memory cell, characterized in that it comprises the operations of: - at the end of each write and erase cycle of the memory cell, reading of erasure conditions of said memory cell during the last erase operation of the cycle, and comparison of said erasure conditions read with a predetermined median erasure value; and determination of writing conditions of the memory cell from the results of the comparison, said writing conditions being applied to the electrodes of the stack during the writing operations of the following writing and erasing cycle so as to to limit the generation of faults in the dielectric material.
    [2" id="c-fr-0002]
    2. Method according to claim 1, characterized in that the writing conditions include a writing voltage value (Vset) applied between the electrodes of each memory cell, for a constant period, so that the dielectric material switches from l '' highly resistive state (HRS) in the weakly resistive state (LRS).
    [3" id="c-fr-0003]
    3. Method according to claim 1, characterized in that the writing conditions include a duration of application (Tset) of a voltage of constant value between the electrodes of each memory cell, so that the dielectric material switches from the highly resistive state (HRS) in weakly resistive state (LRS).
    [4" id="c-fr-0004]
    4. Method according to any one of claims 1 to 3, characterized in that the median erasure value follows a predetermined dependence law (Ld) connecting the writing conditions and the erasing conditions.
    [5" id="c-fr-0005]
    5. Method according to claim 4, characterized in that the dependence law (Ld) is calibrated prior to any writing and erasing cycle.
    [6" id="c-fr-0006]
    6. Method according to any one of claims 1 to 5, characterized in that each write and erase cycle comprises an alternating assembly of at least one write operation and at least one erase operation.
    [7" id="c-fr-0007]
    7. Method according to any one of claims 1 to 6, characterized in that the erasure conditions read are memorized at least partially until the next write and erase cycle, in at least one memory cell of the memory.
    [8" id="c-fr-0008]
    8. Device for programming a non-volatile rewritable memory comprising a programming circuit connected to the electrodes of each memory cell, characterized in that it implements the method according to any one of claims 1 to 7.
    [9" id="c-fr-0009]
    9. Device according to claim 8, characterized in that the programming circuit comprises a plurality of voltage generators capable of each generating at least one write and / or erase voltage value.
    [10" id="c-fr-0010]
    10. Device according to claim 8, characterized in that the programming circuit comprises at least one voltage generator connected to dividing bridges.
    [11" id="c-fr-0011]
    11. Device according to claim 9 or 10, characterized in that the programming circuit comprises at least one voltage generator connected to at least one counter and / or a clock capable of modulating a duration of application of a value voltage constant on the electrodes.
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    同族专利:
    公开号 | 公开日
    EP3401915A1|2018-11-14|
    EP3401915B1|2020-12-09|
    FR3066308B1|2021-07-30|
    US20180330786A1|2018-11-15|
    US10388376B2|2019-08-20|
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    法律状态:
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    2018-11-16| PLSC| Search report ready|Effective date: 20181116 |
    2019-05-31| PLFP| Fee payment|Year of fee payment: 3 |
    2020-05-30| PLFP| Fee payment|Year of fee payment: 4 |
    2021-05-31| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1754043|2017-05-09|
    FR1754043A|FR3066308B1|2017-05-09|2017-05-09|PROCESS FOR MANAGING THE ENDURANCE OF A NON-VOLATILE REWRITING MEMORY AND DEVICE FOR PROGRAMMING SUCH A MEMORY|FR1754043A| FR3066308B1|2017-05-09|2017-05-09|PROCESS FOR MANAGING THE ENDURANCE OF A NON-VOLATILE REWRITING MEMORY AND DEVICE FOR PROGRAMMING SUCH A MEMORY|
    EP18170980.9A| EP3401915B1|2017-05-09|2018-05-07|Method for managing the endurance of a non-volatile rewritable memory and device for programming such a memory|
    US15/975,249| US10388376B2|2017-05-09|2018-05-09|Method for managing the endurance of a non-volatile rewritable memory and device for programming such a memory|
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